Depletion V-groove MOS (VMOS) power transistors

A new depletion MOS transistor is proposed. The structure uses anisotropic etching to define the channel in an n/p epitaxial silicon slice. A simple planar model is developed to explain the characteristics of the devices and is verified by measurements on experimental structures.Power devices are fabricated to illustrate the power capability of the structure. Parameters measured for this structure include: junction temperature, d.c. power dissipation, distortion, ac output power, efficiency. The devices were found to be capable of delivering up to 12W with a cutoff frequency of 80 MHz.     

Depletion m.o.s. power transistors

A new depletion m.o.s. transistor is proposed. The structure uses anisotropic etching to define the channel in an n?p epitaxial silicon slice. The fabrication, characteristics and power capabilities of the device are discussed.     

Algebraic Methods for Optimizing Constant Multiplications in Linear Systems

Constant multiplications can be efficiently implemented in hardware by converting them into a sequence of nested additions and shift operations. They can be optimized further by finding common subexpressions among these operations. In this work, we present algebraic methods for eliminating common subexpressions. Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic. In this work we use the concepts of two of these methods, namely rectangle covering and fast extract (FX) and adapt them to the problem of optimizing linear arithmetic expressions. The main advantage of using such methods is that we can optimize systems consisting of multiple variables, which is not possible using the conventional optimization techniques. Our optimizations are aimed at reducing the area and power consumption of the hardware, and experimental results show up to 30.3% improvement in the number of operations over conventional techniques. Synthesis and simulation results show up to 30% area reduction and up to 27% power reduction. We also modified our algorithm to perform delay aware optimization, where we perform common subexpression elimination such that the delay is not exceeded beyond a particular value.

Long wash cycle duration as a potential for saving energy in laundry washing

Reducing water temperatures in the wash phase of a washing programme and increasing the overall cycle durations are the latest trends in decreasing energy consumption of washing programmes, particularly for the so-called Standard programmes. This paper discusses the importance of saving energy in laundry washing, reasonable cycle duration for consumers and the link between saving energy and the duration of the wash cycle from a consumer point of view. This enables manufacturers to design appliances which are appreciated by the users. Information on consumers’ washing behaviour, experiences, habits and opinions concerning wash cycle duration was collected through a semi-representative survey in 11 European countries in 2015, with more than 5000 participants. The primary outcome of the study is that European consumers are willing to save water and energy in a laundry washing but are reluctant to use long programme cycles since they do not believe that the long cycles could be energy-saving.     

Jammer target discrimination based on local variance of signal histogram in tracking radar and its implementation

In this article, the effects of the number of quantization levels and the sampled signal are considered in the airborne digital radio frequency memory (DRFM). A different model of analog-to-digital conversion is proposed. The histogram of the proposed model is utilized to release synchronization of signals for integration. Then, the local variance technique is used to highlight the differences between a continuous signal and the sampled pre-quantized DRFM signal. Furthermore, the effects of analog reconstruction filter on a DRFM signal are considered. Simulation results show the efficiency and robustness of the proposed method. Finally, a hardware implementation is provided to prove the proposed method.